Sheffield, UK – 20 May 2025. SureCore, the leading memory specialist, has announced the expansion of its sureFIT design service to include AI applications, using its memory design expertise to help AI ...

COMPUTEX - May 19, 2025 — NVIDIA today unveiled NVIDIA NVLink Fusion™ — new silicon that lets industries build semi-custom AI infrastructure with the vast ecosystem of partners building with NVIDIA ...

In a landscape defined by AI acceleration , chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC ...

An interesting data point presented by analyst Richard Wawrzyniak of the SHD Group highlighted the growing maturity and penetration of RISC-V technology: an expected flip from license-driven revenue ...

This strategic collaboration will leverage Synopsys' expertise in silicon IPs to assist in the development of bespoke AI silicon, forming the foundation for advanced compute clusters aimed at deliveri ...

Acquisition enables System-on-a-Chip (SoC) designers to accelerate design closure and enhance functional and structural constraint correctness with industry-proven timing constraints management Plano, ...

The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides ...

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ac- ...

Brno, Czech Republic, and Seoul, Korea – April 23 rd, 2018 – Codasip, the leading supplier of RISC-V ® embedded processor IP, announced today that Dongwoon Anatech, a technology leader in analog and ...

The New Wave Design and Verification (New Wave DV) 1394b PHY core provides a complete IP solution for the PHY layer of the 1394b protocol. The core includes all functionality needed to meet the 1394b ...

The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS ...

The I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I2C Master/Slave core provide a generic ...