Acquisition enables System-on-a-Chip (SoC) designers to accelerate design closure and enhance functional and structural constraint correctness with industry-proven timing constraints management Plano, ...

An interesting data point presented by analyst Richard Wawrzyniak of the SHD Group highlighted the growing maturity and penetration of RISC-V technology: an expected flip from license-driven revenue ...

This strategic collaboration will leverage Synopsys' expertise in silicon IPs to assist in the development of bespoke AI silicon, forming the foundation for advanced compute clusters aimed at deliveri ...

In a landscape defined by AI acceleration , chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC ...

In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from ...

The Samsung SAFE™ program is designed to foster close collaboration between Samsung Foundry and its partners, encouraging innovation and efficiency across the semiconductor design ecosystem. By ...

The report states that memory companies are taking a cautious approach to adopting high-NA EUV technology, largely due to their long-term DRAM roadmaps. According to plans from Samsung and SK hynix, ...

Keysight Technologies, Inc. (NYSE: KEYS), announced that its Quantum Control System (QCS) has been selected as the control system embedded within Fujitsu and RIKEN’s recently developed 256-qubit ...

Against this backdrop, the open-standard instruction set architecture (ISA) known as RISC-V is emerging as a pivotal choice, offering the potential to reshape the semiconductor landscape in Europe and ...

This is not an exhaustive list of the quantum computing companies that have published quantum roadmaps, nor is it a list of all the companies that are busy working toward quantum advantage, but just ...

Flow Computing in Finland has started alpha testing of a RISC-V compiler for its Parallel Processing Unit (PPU) AI block.

The UCIe Consortium’s Universal Chiplet Interconnect Express (UCIe) specification is in its second iteration. It targets designs built around chiplets providing the interconnect between die. The ...